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INTEGRATED CIRCUITS
DATA SHEET
TDA9840 TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
Product specification Supersedes data of 1995 Mar 21 File under Integrated Circuits, IC02 1998 Jul 03
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
FEATURES * Supply voltage 5 to 8 V * De-emphasis * Source selector * Level and stereo matrix adjustment possible via the I2C-bus * I2C-bus transceiver * AF inputs for NICAM or AM sound (standard L) * AF outputs for Main and SCART * AF input and output signals selectable via the I2C-bus * Information for identified transmission mode is readable via I2C-bus * Software is compatible with the TDA8415/16/17 * Quartz oscillator and clock generator * Three digital PLL, alignment-free * Two digital integrators, alignment-free * Stabilizer circuit for ripple rejection and constant output signals * ESD protection of all pins. ORDERING INFORMATION PACKAGE TYPE NUMBER NAME TDA9840 TDA9840T DIP20 SO20 DESCRIPTION plastic dual in-line package; 20 leads (300 mil) plastic small outline package; 20 leads; body width 7.5 mm GENERAL DESCRIPTION
TDA9840
The TDA9840 is a stereo/dual sound processor for TV and VTR sets. Its identification ensures safe operation by using internal digital PLL technique with extremely small bandwidth, synchronous detection and digital integration (switching time maximum 2.3 s; identification concerning the main functions).
VERSION SOT146-1 SOT163-1
1998 Jul 03
2
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
QUICK REFERENCE DATA SYMBOL VP IP Vi(rms) Vo(rms) Vo(rms) PARAMETER supply voltage (pin 18) supply current (pin 18) nominal input signal voltage (Vi 1, Vi 2, Vi 3) (RMS value) nominal output signal voltage (RMS value) clipping level of the output signal voltages (RMS value) 54% modulation THD 0.3% 54% modulation THD 1.5% VP = 5 V VP = 8 V Gv stereo control range for Vi 1 (0.1 dB steps) level control range for Vi 2 (0.5 dB steps) Vi pil S/N(W) THD Tamb fident input voltage sensitivity of pilot frequency weighted signal-to-noise ratio total harmonic distortion operating ambient temperature range identification window width normal mode STEREO DUAL fast mode STEREO DUAL tident(on) total identification time ON normal mode STEREO DUAL fast mode STEREO DUAL Vi tuner fpil identification voltage sensitivity pull-in frequency range of pilot PLL f = 10.008 MHz lower side upper side -296 302 - - 0.175 0.175 - - - 28 0.35 0.35 - - 3.8 5.8 - - 2.0 2.3 - - unmodulated 1.4 2.4 +2.4 -2.3 +2.4 -1.9 5 66 - 0 1.6 2.65 +2.5 -2.4 +2.5 -2.0 - 75 0.2 - CONDITIONS MIN. 4.5 15.5 - - TYP. 5 16.5 250 500
TDA9840
MAX. 8.8 20.5 - -
UNIT V mA mV mV
- - +2.6 -2.5 +2.6 -2.1 100 - 0.3 +70 2.0 2.3 3.8 5.8 2.3 2.0 1.1 1.0 - -296 302
V V dB dB dB dB mV dB % C Hz Hz Hz Hz s s s s dBV Hz Hz
"CCIR468-3"
1998 Jul 03
3
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1998 Jul 03
L+R , A 2 Vi 1 250 mV RMS (from 1st SC) 2.2 F 7 10 k 40 k
-2 dB
BLOCK DIAGRAMS
Philips Semiconductors
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
CD1
Vi 3 Vi 4 CD2
10 nF 2.2 F 5% 15 17 25 k 25 k
500 mV RMS
10 nF 5%
2.2 F
9 10 25 k
5 k
6 dB
500 mV RMS
14
Vo 1 MAIN
0 to 4.5 dB 0 to -0.4 dB A/MONO L 10 k 10 k
L/A/MONO 250 mV RMS
6 dB
25 k
500 mV RMS
13
Vo 2
250 mV RMS (from 2nd SC) Vi 2 8 R, B 2.2 F 10 k
40 k
-2 dB
5 k 0 to 4.5 dB
R/B 250 mV RMS
6 dB
500 mV RMS
12
Vo 3 SCART
6 dB 30 k level stereo
500 mV RMS
11
Vo 4
TDA9840
mute
LEVEL AND STEREO ADJUSTMENT 47 pF
DIGITAL PLL AND DEMODULATOR
DIGITAL INTEGRATOR
DUAL bit 20 I 2 C-BUS CONTROL 1 SCL SDA
4
V i pil 3.3 nF tan 0.002 CDCL 2.5 mH Q0 = 70 4 100 nF CAGC 10 F CLP 10 nF 3 2 5
DIGITAL PLL 25 k 25 k
DIGITAL PLL AND DEMODULATOR
DIGITAL INTEGRATOR
STEREO bit
OSCILLATOR Vref
GENERATION OF REFERENCE VOLTAGES 6 18 16
POWER-ON RESET
CONTROL LOGIC
19 XTAL 10 MHz 1/2 VP Cref 100 F / 16 V
Product specification
GND
MBE457
TDA9840
Input and output levels are nominal values. They are related to the SCART norm. (AM: m = 0.54, FM: f = 27 kHz).
VP
Fig.1 Block diagram of the bipolar TV/VTR-stereo decoder.
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1998 Jul 03
Vi 1 L+R , A 2 2.2 F 7 10 k 40 k
-2 dB
Philips Semiconductors
Vi 3 Vi 4 CD1 10 nF 5% CD2 10 nF 5% 15 17 2.2 F
9 25 k 25 k
500 mV RMS
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
2.2 F
10 25 k
5 k
250 mV RMS (from 1st SC)
6 dB
500 mV RMS
14
Vo 1 MAIN
0 to 4.5 dB 0 to -0.4 dB A/MONO L 10 k 10 k
L/A/MONO 250 mV RMS
6 dB
25 k
500 mV RMS
13
Vo 2
250 mV RMS (from 2nd SC) Vi 2 8 R, B 2.2 F 10 k
40 k
-2 dB
5 k 0 to 4.5 dB
R/B 250 mV RMS
6 dB
500 mV RMS
12
Vo 3 SCART
6 dB 27 k level stereo
500 mV RMS
11
Vo 4
TDA9840
mute
LEVEL AND STEREO ADJUSTMENT 180 pF
DIGITAL PLL AND DEMODULATOR
DIGITAL INTEGRATOR
DUAL bit 20 I 2 C-BUS CONTROL 1 SCL SDA
5
1.8 nF 2% tan 0.01 CDCL CAGC CLP
V i pil 4.7 mH 5% Q0 = 25 100 nF
5 DIGITAL PLL 4 25 k 25 k DIGITAL PLL AND DEMODULATOR DIGITAL INTEGRATOR
STEREO bit
2 10 F 3 10 nF
OSCILLATOR Vref
GENERATION OF REFERENCE VOLTAGES 6 18 16 GND
POWER-ON RESET
CONTROL LOGIC
19 XTAL 1/2 VP Cref 100 F / 16 V
MBE458
Product specification
10 MHz Input and output levels are nominal values. They are related to the SCART norm. (AM: m = 0.54, FM: f = 27 kHz).
VP
The components of the external LC band-pass filter have the following order-No.: Philips Germany only No: 4312 020 17525 or Fastron Sdn. Bha., Malaysia type SMCC 472 J for L = 4.7 mHz (5%) Philips Components No: 2222 429 71802, C = 1.8 nF (2%).
TDA9840
Fig.2 Block diagram of the bipolar TV/VTR-stereo decoder with fixed coil (alignment-free).
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
PINNING SYMBOL PIN SDA CAGC CLP CDCL Vi pil Cref Vi 1 Vi 2 Vi 3 Vi 4 Vo 4 Vo 3 Vo 2 Vo 1 CD1 GND CD2 VP XTAL SCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I2C-bus DESCRIPTION data input/output AGC capacitor of pilot frequency amplifier identification low-pass capacitor DC loop capacitor pilot frequency input voltage capacitor of reference voltage (1
2VP)
fpage
TDA9840
SDA CAGC CLP CDCL V i pil Cref Vi 1 Vi 2 Vi 3
1 2 3 4 5
20 SCL 19 XTAL 18 V P 17 CD2 16 GND
AF input signal Vi 1 (from 1st sound carrier) AF input signal Vi 2 (from 2nd sound carrier) AF input signal Vi 3 (NICAM or AM sound (standard L)) AF input signal Vi 4 (NICAM) AF output signal Vo 4 (SCART) AF output signal Vo 3 (SCART) AF output signal Vo 2 (main) AF output signal Vo 1 (main) 50 s de-emphasis capacitor of AF Channel 1 ground (0 V) 50 s de-emphasis capacitor of AF Channel 2 supply voltage (+5 to +8 V) 10 MHz crystal input I2C-bus clock input
TDA9840
6 7 8 9
15 CD1 14 Vo 1 13 Vo 2 12 Vo 3 11 Vo 4
Vi 4 10
MBE459
Fig.3 Pin configuration.
1998 Jul 03
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
FUNCTIONAL DESCRIPTION The TDA9840 (see Fig.1) receives the signals from the FM-demodulators in a TV two sound-carrier system. The circuit is realized by the H00485 bipolar process. The IC is intended for use in economic TV and VTR receivers. Therefore optimum relationship between integration of functions and use of external components has been striven for. Additionally a new type of identification circuit has been developed. AF signal handling The input AF signals, derived from the two sound carriers, are processed in analog form using operational amplifiers.The circuit incorporates level- and stereo-adjustment to correct the spreading in the FM detector output levels. Dematrixing uses the technique of two amplifiers processing the AF signals. Finally, a source selector provides the facility to route the mono signal through to the outputs (`forced mono'). De-emphasis is performed by two RC low-pass filter networks with internal resistors and external capacitors. This provides a frequency response with the tolerances given in Fig.4. A source selector, controlled via the I2C-bus, allows selection of the different modes of operation in accordance with the transmitted signal. The device was designed for a nominal input signal (FM: 54% modulation is equivalent to f = 27 kHz / AM: m = 0.54) of 250 mV RMS (Vi 1, Vi 2), respectively 500 mV RMS (Vi 3,Vi 4). A nominal gain of 6 dB for Vi 1 and Vi 2 signals and 0 dB for Vi 3 and Vi 4 signals is built-in. By using rail-to-rail operational amplifiers, the clipping level (THD 1.5%) is 1.6 V RMS for VP = 5 V and 2.65 V RMS for VP = 8 V at outputs Vo 1, Vo 2,Vo 3 and Vo 4. Care has been taken to minimize switching plops. Also total harmonic distortion and random noise are considerably reduced. Identification The pilot signal is fed via an external RC high-pass filter and single tuned LC band-pass filter to the input of a gain controlled amplifier. The external LC band-pass filter in combination with the external RC high-pass filter should have a loaded Q-factor of about 40 to 50 to ensure the highest identification sensitivity. By using a fixed coil (5%) to save the alignment (see Fig.2), a Q-factor of about 12 is proposed. This may cause a loss in sensitivity of about 2 to 3 dB. A digital PLL circuit generates a reference carrier, which is synchronized with the pilot carrier. This reference carrier and the gain controlled pilot signal
TDA9840
are fed to the AM-synchronous demodulator. The demodulator detects the identification signal, which is fed through a low-pass filter with external capacitor CLP (pin 3) to a Schmitt-trigger for pulse shaping and suppression of low level spurious signal components. This is a measure against mis-identification. The identification signal is amplified and fed through an AGC low-pass filter with external capacitor CAGC (pin 2) to obtain the AGC voltage for controlling the gain of the pilot signal amplifier. The identification stages consist of two digital PLL circuits with digital synchronous demodulation and digital integrators to generate the stereo or dual sound identification bits which can be read out via the I2C-bus. A 10 MHz quartz crystal oscillator provides the reference clock frequency. The corresponding detection bandwidth is larger than 50 Hz for the pilot carrier signal, so that fp-variations from the transmitter can be tracked in case of missing synchronisation with the horizontal frequency fH. However the detection bandwidth for the identification signal is made small (approximately 1 Hz) to reduce mis-identification. Figure 2 shows an example of the alignment-free fp band-pass filter. To achieve the required QL of approximately 12, the Q0 at fp of the coil was chosen to be approximately 25 (effective Q0 including PCB influence). Using coils with other Q0, the RC-network (RFP, CFP) has to be adapted accordingly. It is assumed that the loss factor tan of the resonance capacitor is 0.01 at fp. Copper areas under the coil might influence the loaded Q and have to be taken into account. Care has also to be taken in environments with strong magnetic fields when using coils without magnetic shielding. I2C-bus transceiver The complete IC is controlled by a microcomputer via the I2C-bus. The built-in I2C-bus transceiver transmits the identification result to the I2C-bus and receives the control data for the source selector and level control. The I2C-bus protocol is given in Tables 2 to 12 respectively. The data transmission between the microcontroller and the other I2C-bus controlled ICs is not disturbed, when the supply voltage of the TDA9840 is not connected or when powering up or down. Finally, a Schmitt-trigger is built-in the SDA/SCL interface to suppress spikes from the I2C-bus.
1998 Jul 03
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
Power supply The different supply voltages and currents required for the analog and digital circuits are derived from an internal band-gap reference circuit. The AF reference voltage is 1 V . For a fast setting to 1 V an internal start-up circuit 2P 2P is added. A good ripple rejection is achieved with the external capacitor Cref = 100 F/16 V in conjunction with the high ohmic input of the 12VP pin (pin 6). Additional DC-load on this pin is prohibited. Power-on reset When a power-on reset is activated by switching on the supply voltage or because of a supply voltage breakdown, the 117/274 Hz DPLL, the 117/274 Hz integrator and the registers will be reset. Both AF channels (Main and SCART) are muted. Fast mode / test mode
TDA9840
The TDA9840 has a fast mode (test mode) to reduce the integration time of the 117/274 Hz integrator from approximately 1 to 0.5 s. ESD protection All pins are ESD protected. The protection circuits represent the latest state of the art. Internal circuit The internal pin loading diagram is given in Fig.7.
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VP Vi Vi Tstg Tamb Vesd Note 1. Charge device model class B: discharging a 200 pF capacitor through a 0 series resistor. THERMAL CHARACTERISTICS SYMBOL Rth j-a DIP20 SO20 PARAMETER thermal resistance from junction to ambient in free air 73 90 K/W K/W VALUE UNIT PARAMETER supply voltage (pin 18) voltage at pins 1 and 20 voltage at pins 2 to 15, 17 and 19 storage temperature operating ambient temperature electrostatic handling for all pins note 1 CONDITIONS MIN. -0.3 -0.3 -0.3 -25 0 - MAX. 10 5.5 VP +150 +70 300 V V V C C V UNIT
1998 Jul 03
8
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
TDA9840
CHARACTERISTICS VP = 5 V; Tamb = +25 C; nominal input signal Vi 1, 2 = 0.25 V RMS value (FM: 54% modulation is equivalent to f = 27 kHz); nominal input signal Vi 3, 4 = 0.5 V RMS value (AM: m = 0.54); nominal output signal Vo 1, 2, 3, 4 = 0.5 V RMS value; fAF = 1 kHz; Vi pil = 16 mV RMS value; fpil = 54.6875 kHz (identification frequencies: stereo = 117.48 Hz, dual = 274.12 Hz), 50 s pre-emphasis; noise measurement in accordance with "CCIR468-3", working oscillator frequency f = 10.008 MHz; currents into the IC positive; measured in test circuit according to Fig.5; unless otherwise specified. SYMBOL Supply VP IP Ptot Vn(DC) Vref(DC) lL(DC) supply voltage (pin 18) supply current (pin 18) total power dissipation DC voltage (pins 7 to 15 and 17) DC reference voltage (pin 6) DC leakage current (pin 6) 4.5 15.5 69.75
1 1 2VP 2VP
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
5 16.5 82.5
1 1 2VP 2VP
8.8 20.5 180.4
1 1 2VP 2VP
V mA mW V V A + 0.1 + 0.1
- 0.1 - 0.1
- -
-
1 -
AF Inputs; Vi 1 and Vi 2 (pins 7 and 8) Vi(rms) Vi(rms) nominal input signal voltage (RMS value) clipping voltage level (RMS value) 54% modulation THD 1.5%; note 1 VP = 5 V VP = 8 V THD 1.5%; note 2 VP = 5 V VP = 8 V Gv AF signal voltage gain G = Vo/Vi; note 3 only at pin 7 maximum 49 steps only at pin 8 maximum 9 steps see Fig.4 Gv (Vo1) stereo control range nominal step Gv (Vo2) level control range nominal step Ri Rdeem input resistance internal de-emphasis resistor (pins 15 and 17) 0.780 1.300 5 +2.4 -2.3 - +2.4 -1.9 - 40 4.25 0.900 1.500 6 +2.5 -2.4 0.1 +2.5 -2.0 0.5 50 5.0 - - 7 +2.6 -2.5 - +2.6 -2.1 - 60 5.75 V V dB dB dB dB dB dB dB k k 0.625 1.050 0.715 1.200 - - V V 0.25 V
Additional AF input pin (pins 9 and 10) Vi(rms) Vi(rms) nominal input signal voltage (RMS value) clipping voltage level (RMS value) 54% modulation THD 1.5% VP = 5 V VP = 8 V Gv Ri 1998 Jul 03 AF signal voltage gain input resistance 9 G = Vo/Vi; note 3 1.25 2.10 -1 40 1.40 2.35 0 50 - - 1 60 V V dB k - 0.5 - V
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
SYMBOL PARAMETER CONDITIONS THD 0.3%; 54% modulation THD 1.5% VP = 5 V VP = 8 V Ro CL RL B B-3 dB THD S/N(W) cr output resistance load capacitor on output load resistor on output (AC-coupled) frequency response (bandwidth) frequency response total harmonic distortion weighted signal-to-noise ratio crosstalk attenuation for DUAL STEREO mute VDC mute attenuation change of DC level output voltage between any two modes of operation power supply ripple rejection DC output current noise from I2C-bus note 6 fi = 40 to 20000 Hz; note 4 -3 dB; note 4 note 3 1.4 2.4 150 - 10 -0.5 300 - 66 1.6 2.65 250 - - - 350 0.2 75 - - 350 1.5 - +0.5 400 0.3 - - MIN. TYP. -
TDA9840
MAX.
UNIT
AF outputs (pins 11 to 14) Vo(rms) Vo(rms) nominal output signal voltage (RMS value) clipping voltage level (RMS value) 0.5 V
V V nF k dB kHz % dB
"CCIR468-3" (quasi-peak)
notes 3 and 5 Zs 1 k Zs 1 k Zs 1 k; note 3 after switching
70 40 76 -
75 45 80 -
- - - 10
dB dB dB mV
PSRR IO(DC) I2C fr f
fr = 70 Hz; see Fig.6
50 - -
65 - 90
- 20 80
dB A dB
10 MHz crystal oscillator (pin 19) series resonant frequency of crystal (fundamental mode) working oscillator frequency (running in parallel resonance mode) CL = 20 pF over operating temperature range including ageing and influence of drive circuit even at extremely low drive level (<1 pW) over operating temperature range with C0 = 6 pF 9.995 9.988 10.008 10.008 10.021 10.028 MHz MHz
Rr
equivalent crystal series resistance
-
60
200
Rn C0 C1
crystal series resistance of unwanted mode crystal parallel capacitance crystal motional capacitance with Rr 100
2 x Rr - -
- 6 25
- 10 50
pF fF
1998 Jul 03
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
SYMBOL PXTAL VOSC(p-p) PARAMETER level of drive in operation oscillator operating voltage (peak-to-peak value) CONDITIONS - 500 MIN. - 550 TYP. 5 600
TDA9840
MAX.
UNIT W mV
Pilot processing Vi pil(rms) Ri pil m fpil pilot input voltage level at pin 5 unmodulated (RMS value) pilot input resistance modulation depth pilot PLL pull-in frequency range (referred to fpil = 54.6875 kHz) AM f = 9.988 MHz lower side upper side f = 10.008 MHz lower side upper side f = 10.028 MHz lower side upper side tpil fLP R3 V4(rms) QL pilot PLL pull-in time low-pass frequency response low-pass output resistance identification threshold voltage (RMS value) loaded quality factor of resonance circuit loaded quality factor of resonance circuit with fixed coil tacqui AGC AGC acquisition time high sensitivity sensitivity loss 2 to 3 dB; see Fig.2 Vi pil(rms) switched from 0 to 100 mV RMS value -3 dB -188 411 0 450 18.75 - 40 - - - - 600 25 - - 12 -188 411 1.7 750 31.25 70 50 - Hz Hz ms Hz k mV -296 302 - - -296 302 Hz Hz -405 192 - - -405 192 Hz Hz 5 500 25 - 1000 50 100 - 75 mV k %
-
-
0.1
s
Identification (internal functions) Vi tuner C/N H identification voltage sensitivity note 7 (pin 5) pilot carrier-to-noise ratio for start of identification hysteresis note 8 note 7 - - - 28 33 - - - 2 dBV dB/Hz dB
1998 Jul 03
11
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
SYMBOL fdet PARAMETER pull-in frequency range of identification PLL (referred to fdet STEREO = 117.48 Hz and fdet DUAL = 274.12 Hz) CONDITIONS normal mode lower side STEREO DUAL normal mode upper side STEREO DUAL fast mode lower side STEREO DUAL fast mode upper side STEREO DUAL tdet pull-in time of identification PLL (referred to fdet STEREO = 117.48 Hz and fdet DUAL = 274.12 Hz) normal mode STEREO DUAL fast mode STEREO DUAL fident identification window frequency width (referred to fdet STEREO = 117.48 Hz and fdet DUAL = 274.12 Hz) normal mode; note 9 STEREO DUAL fast mode; note 9 STEREO DUAL tintegr tident(on) integrator time constant total identification time on normal mode fast mode normal mode; note 10 STEREO DUAL fast mode; note 10 STEREO DUAL tident(off) total identification time off normal mode; note 11 STEREO DUAL fast mode; note 11 STEREO DUAL 0.3 0.3 - - 0.8 0.8 0.6 0.6 - - 1.6 1.6 0.175 0.175 - - 1.1 1.0 0.35 0.35 - - 2.3 2.0 3.8 5.8 0.94 0.47 - - - - 3.8 5.8 0.94 0.47 2.0 2.3 - - 2.0 2.3 0 0 - - 0.57 0.25 0 0 - - 1.35 0.72 1.15 2.05 - - 1.15 2.05 -0.89 -2.05 - - 0.69 0.69 - - 0.69 0.69 -0.38 -0.69 - - MIN. TYP.
TDA9840
MAX.
UNIT
-0.38 -0.69
Hz Hz
Hz Hz Hz Hz Hz Hz s s s s Hz Hz Hz Hz s s s s s s s s s s
-0.89 -2.05
1998 Jul 03
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
SYMBOL PARAMETER CONDITIONS MIN. TYP.
TDA9840
MAX.
UNIT
I2C-bus transceiver (pins 1 and 20) fCI clock frequency 0 -0.3 3.0 4.7 4.0 - - - - -0.3 3.0 - - 0.25 - -3 - - - - - - - - - - - - - - - - - - 100 kHz
I2C-bus: SCL (pin 20) VIL VIH tlow thigh tr tf IIL IIH LOW level input voltage HIGH level input voltage timing LOW period timing HIGH period rise time fall time LOW level input current HIGH level input current 1.5 5.5 - - 1 0.3 -10 10 V V s s s s A A
I2C-bus: SDA (pin 1) VIL VIH tr tf tsu IIL IOL IIH Notes 1. Input control amplifiers with Gv = 0 dB. 2. Input control amplifiers with Gv = -2 dB. 3. Vo = 0.5 V RMS value; f = 1 kHz; input control amplifiers with Gv = 0 dB. 4. Without de-emphasis capacitors with respect to nominal gain. 5. In dual mode: A (B)-signal into B (A) channel. In stereo mode: R-signal into left channel; L-signal = 0. 6. Test procedure tbf (same as TDA9855). 7. Tuner input signal, measured with PCALH reference front end (12EMF, 75 , 2T/20T/white bar, 100% video) and PC/SC1 = 13 dB; PC/SC2 = 20 dB. The pilot band-pass has to be aligned. 8. Bandwidth of the pilot BP-filter B-3 dB = 1.2 kHz. Vi 2 input driven with identification-modulated pilot carrier and white noise. 9. Identification window is defined as total pull-in frequency range (lower plus upper side) of identification PLL (steady detection) plus window increase due to integrator (fluctuating detection). 10. The maximum total system identification time ON is equal to tident(on) plus tacqui AGC plus tI2C read-out. 11. The maximum total system identification time OFF is equal to tident(off) plus tI2C read-out. LOW level input voltage HIGH level input voltage rise time fall time data set-up time LOW level input current LOW level output current HIGH level input current 1.5 5.5 1 0.3 - -10 - 10 V V s s s A mA A
1998 Jul 03
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
I2C-BUS PROTOCOL FOR THE TV AND VTR STEREO/DUAL SOUND PROCESSOR TDA9840 The TDA9840 has an I2C-bus interface with five registers: status, test, switch, level and stereo adjustment register controlled by a microcontroller via I2C-bus. The status register can be read and the other registers are write registers. The status byte represents the transmitter status detected by the identification circuit and the power-on reset status. The switch register controls the source selectors of the AF signal part, and the level and stereo adjustment register set the input level and stereo adjustment stage. Additionally, a test register is built-in to reduce the detection time of the identification circuit (test mode, fast mode respectively). I2C-bus transceiver and data-handling (bus specification) The TDA9840 is controlled by a microcomputer via the bidirectional 2-line I2C-bus. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. When the bus is free, both lines are HIGH. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change, when the clock signal on the SCL line is LOW. The set-up and hold times are specified in the Chapter "Characteristics". A HIGH-to-LOW transition of the SDA line, while SCL is HIGH, is defined as the start condition. A LOW-to-HIGH transition of the SDA line, while SCL is HIGH, is defined as the stop condition. The bus transceiver will be reset on the reception of a start condition. The bus is considered to be busy after the start condition. The bus is considered to be free again after a stop condition. Data format transmitter mode For the data transmission no subaddress is to be transmitted, because there is only one read register implemented. So the total number of bytes reduces from three to two. The second byte represents the status of the IC. Status register (see Table 4) The bit D7 (PONRES) represents the status of the IC and indicates whether the power-on reset was activated by switching-on the supply voltage or a supply voltage breakdown. If so, the I2C-bus transceiver, the digital PLLs and integrators are initialized and the PONRES bit is set to 1998 Jul 03 14
TDA9840
HIGH. After a successful reading of the status register, the bit D7 will be reset to LOW. The bits D5 and D6 represent the transmitter status detected by the identification circuit (stereo, dual or mono transmission). The other bits are set to 0 (default). Data format for the receiver Table 1 Registers for receiver mode (see Table 6) REGISTER Switch register Port register Level adjustment register Stereo adjustment register Test register (00)HEX (01)HEX (without function) (02)HEX (03)HEX (04)HEX VALUE
The port register is without function, because this IC has no control ports as TDA8415/6/7. A data byte for the subaddress (01)HEX will not be stored in any register. An acknowledge will be sent to the microcontroller. The first byte of the data transmission is the slave address and the second byte is the subaddress indicating the data register in which the data shall be stored. Starting from subaddress (00)HEX the n-th data byte will automatically be stored under subaddress n - 1. All 8 bits of the subaddress are decoded by the device. The subaddresses from (04)HEX to (FF)HEX are forbidden for the user. If the I2C-bus transceiver receives subaddresses from (05)HEX to (FF)HEX, no acknowledge will be sent back to the microcontroller. Switch register The source selector is controlled by the switch register. Table 7 shows the modes of operation. Note, that in the event of the external operation mode, no further selection is possible.
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
Level adjustment register The information about the level adjustment of the AF channel Vi 2 (pin 8) is stored in the level adjustment register (see Table 10). There are 10 steps (positions) of the AF level adjustment stage. The level range is from 2.5 dB up to -2.0 dB in 0.5 dB steps. After a power-on reset, the data byte of the level adjustment register will be set to (00)HEX: 0 dB gain at the AF input Vi 2. Stereo adjustment register The information about the stereo adjustment of the AF channel Vi 1 (pin 7) is stored in the stereo adjustment register (see Table 11). There are 50 steps (positions) of the AF stereo adjustment stage. The stereo range is from 2.5 dB up to -2.4 dB in 0.1 dB steps. After a power-on reset, the data byte of the stereo adjustment register will be set to (00)HEX: 0 dB gain at the AF input Vi 1. Test register (also used for fast mode) Table 12 shows the meaning of the test register. The integration time of the integrator is approximately 1 s (normal mode, default). If the data byte of this register is set to HIGH, the integration time is reduced from approximately 1 to approximately 0.5 s (fast mode, test mode). The pull-in ranges of the identification PLLs are changed to: Stereo: -0.89/+1.15 Hz Dual: 2.05 Hz. If the integration time of the integrator is switched from one mode to the other (i.e. from fast mode/test mode to normal mode), the status register bits D5 and D6 might set to zero internally (MONO). Therefore, the previous status register information has to be stored by the microcontroller until the transmitter status is detected again by the identification circuit (now in the new mode) the first time. The data byte of the test register can be reset in two different ways to (00)HEX: integration time approximately 1 s, normal mode: * after a power-on reset, for instance by switching the power supply Vp off and on again * data transmission via I2C-bus for the test register (see Table 12). Level and stereo adjustment
TDA9840
For the level and stereo adjustment of both AF channels Vi 1 and Vi 2, the following procedure will be recommended. Level adjustment of the AF channel V * Feeds AF signal at the input Vi 2 * Sets the data byte of the switch register (dual mode) to (1A)HEX * Measures the signal at the outputs Vo 2 or Vo 4 * Adjusts the output level with the level adjustment register. Stereo adjustment of the AF channel Vi 1 * Feeds AF stereo signals at the inputs Vi 1 ((L+R)/2) and Vi 2 (R) * Sets the data byte of the switch register (stereo mode) to (2A)HEX * Measures the crosstalk attenuation between Vo 1 and Vo 2 or Vo 3 and Vo 4 * Adjusts the crosstalk attenuation with the stereo adjustment register. During the stereo adjustment the data byte of the level adjustment register does not change. After the level and stereo adjustment, the bytes of the level and stereo adjustment register must be stored by the microcontroller in a memory. (To avoid mis-adjustment it would be wise to compare the stored bytes with the proper adjustment bytes). If the PONRES bit of the status register will be set to HIGH (see status register) the data bytes for these both registers must be sent out of the memory to the TDA9840 via I2C-bus. Also the data byte of the switch register (see Table 7) must be changed, because the AF outputs are muted.
1998 Jul 03
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
I2C-BUS FORMAT
TDA9840
X is the read/write control bit; X = 0, order to write (the circuit is slave receiver); X = 1, order to read (the circuit is slave transmitter). If more than 1 byte of DATA is transmitted, then auto-increment of the significant subaddress is performed. Table 2 S Table 3 I2C-bus; SLAVE ADDRESS/SUBADDRESS/DATA format SLAVE ADDRESS Explanation of Table 2 BIT S A SUBADDRESS DATA P Table 4 start condition acknowledge, generated by the slave dual sound A/B data byte; see Table 6 stop condition I2C-bus; SLAVE ADDRESS/DATA to read the status byte (X = 1 in the address byte) SLAVE ADDRESS 1000 0101 DATA D7 PONRES D6 ST D5 DS D4 0 D3 0 D2 0 D1 0 D0 0 SLAVE ADDRESS 1000 010X FUNCTION A SUBADDRESS A DATA P
FUNCTION Status byte Table 5
Explanation of Table 4 BIT FUNCTION after a successful reading of the status register after power-on reset or after supply breakdown MONO sound identified DUAL sound identified STEREO sound identified incorrect identification
PONRES = 0 PONRES = 1 ST = 0; DS = 0 ST = 0; DS = 1 ST = 1; DS = 0 ST = 1; DS = 1
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
Table 6 I2C-bus; SUBADDRESS/DATA for writing (X = 0 in the address byte) DATA FUNCTION Switching Without function (note 1) Level adjustment Stereo adjustment Note 1. This byte is acknowledged by the TDA9840. Function of the bits: * SW6 to SW0 input and output AF selection; see Table 7 * LV3 to LV0 level adjustment; see Table 10 * ST5 to ST0 stereo adjustment; see Table 11. Table 7 Data byte to select AF inputs and AF outputs [subaddress (00)HEX] INPUT SIGNAL TRANSMISSION MODE ST/DS/M EXT OUTPUT SIGNAL DATA MAIN SCART D7 0 M S R A B A B D 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 1 D5 0 0 0 1 0 0 0 0 1 D4 0 1 1 0 1 1 1 1 1 D3 0 0 0 1 0 1 0 1 1 D2 0 0 0 0 0 0 1 1 0 V i 1 Vi 2 Vi 3 Vi 4 Vo 1 Vo 2 Vo 3 Vo 4 PIN PIN PIN PIN PIN PIN PIN PIN 7 8 9 10 14 13 12 11 - M S S DUAL DS A A A A External Table 8 - - - - R R B B B B - - - - - - - - - C - - - - - - - - D M S L A A A A C no signal M S R B B B B D M S L A A B B C SUBADDRESS D7 0000 0000 0000 0001 0000 0010 0000 0011 0 0 0 0 D6 SW6 0 0 0 D5 SW5 0 0 ST5 D4 SW4 0 0 ST4 D3 SW3 0 LV3 ST3 D2 SW2 0 LV2 ST2
TDA9840
D1 SW1 0 LV1 ST1
D0 SW0 0 LV0 ST0
D1 0 0 0 1 1 1 1 1 1
D0 0 0 0 0 0 0 0 0 0
HEX 00 10 10 2A 12 1A 16 1E 7A
Sound mute - MONO STEREO M ST
Explanation of Table 7 DESCRIPTION right left ( L + R) -------------------2 dual sound A/B C D M DS ST SIGNAL NICAM mono sound dual sound stereo sound DESCRIPTION NICAM or AM sound (standard L)
SIGNAL R L S A and B
1998 Jul 03
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
Table 9 AF switch configuration INPUT TRANSMITTER STATUS MONO STEREO DUAL External SIGNAL M L R A B C D Table 10 Data byte to select level adjustment [subaddress (02)HEX] GV (dB) +2.5 +2.0 +1.5 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 DATA D7 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 D3 1 1 1 1 1 0 0 0 0 0 D2 1 1 0 0 0 0 0 0 0 1 D1 0 0 1 1 0 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 MAIN M M L or M R or M A B C D OUTPUT
TDA9840
SCART M M L or M R or M A or B A or B C D
HEX 0D 0C 0B 0A 09 00 01 02 03 04
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18
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
Table 11 Data byte to select stereo adjustment [subaddress (03)HEX] GV (dB) +2.5 +2.4 +2.3 +2.2 +2.1 +2.0 +1.9 +1.8 +1.7 +1.6 +1.5 +1.4 +1.3 +1.2 +1.1 +1.0 +0.9 +0.8 +0.7 +0.6 +0.5 +0.4 +0.3 +0.2 +0.1 DATA D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D4 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D3 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 D2 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 GV (dB) 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1.0 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2.0 -2.1 -2.2 -2.3 -2.4 DATA D7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0
TDA9840
D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18
Table 12 Data byte to select integration time [subaddress (04)HEX] DATA FUNCTION Test byte Function of the bits: * INTFU = 0 integrator function enabled * INTFU = 1 integrator function disabled * INT1SN = 0 integration time approximately 1 s (default) * INT1SN = 1integration time approximately 0.5 s. SUBADDRESS D7 0000 0100 X D6 X D5 X D4 X D3 X D2 X D1 INTFU D0 INT1SN
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
TDA9840
+2 VoAF (dB) +1 R: -15%; C: -5%
MED647
0
-1
R: +15%; C: +5%
-2 10
10 2
10 3
10 4
foAF (Hz)
10 5
Fig.4
Tolerance scheme of AF frequency response; de-emphasis with CD1, CD2 = 10 nF (5%), Rinternal = 5 k (15%).
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
TDA9840
handbook, full pagewidth
SDA C AGC 100 F/16 V C ref C LP 10 nF 10 F
1
20 XTAL
SCL 10 MHz
2
19 CVP 10 F VP
3 100 nF 4
18
1/2 V P
C DCL
17
5% C D2 10 nF
50 s de-emphasis
5 47 pF 3.3 nF 2.5 mH 6 30 k AF from 5.5 MHz Vi 1 2.2 F AF from 5.742 MHz Vi 2 2.2 F from external sound source C Vi 3 2.2 F from external sound source D Vi 4 10 9 8 2.2 F 7
16
TDA9840
15 5% C D1 10 nF Vo 1 main 13 Vo 2 50 s de-emphasis
14
12
Vo 3 scart
11
MBE460
Vo 4
Fig.5 Test circuit of the stereo decoder TDA9840.
handbook, full pagewidth
14 VB 10 k 100 F 5 V modulated with 200 mV (p-p) 100 F / 16 V 100 F 6 7 8 9 10 16 VP 13 18
Vo 1 Vo 2 Vo 3 Vo 4 measurements on outputs
TDA9840
12 11
70 Hz
MBE462
Fig.6 Test circuit for measurement of ripple rejection.
1998 Jul 03
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Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
INTERNAL CIRCUITRY
handbook, full pagewidth
TDA9840
+
+
SDA
1
2 k
2 k 20 19 3 pF +5 V
SCL XTAL
+
- + 13 k
5 k
18
VP
+ 3 25 k 1/2 VP
+
CLP
40 A
+ 60 A - +
CDCL
4 + 40 A 5 k 5 k 5 6 25 k
Vi pil Cref
5 k 7 + 10 k
5 k -2 dB
22.5 k
IB
Vi 1
TDA9840
IB AF outputs
40 k
Vi 2
8
10 k
1/2 VP -2 dB
40 k
IB
AF inputs 12 Vo 3
Vi 3
9
1/2 VP 25 k -6 dB
25 k 200 A +
IB
Vi 4
10 25 k
1/2 VP -6 dB
25 k
IB
1/2 VP
VP
MBE461
ESD protection diode for pins 2 to 15, 17 and 19
zener diode protection for pins 1, 18 and 20
Fig.7 Internal circuits.
1998 Jul 03
22
- - + 16 5 k 15 - + + 14 200 A + 13 + 200 A 11 200 A
CAGC
2
25 k
+
+
68 A
5 k
17
C
D2
GND
C
D1
Vo 1
Vo 2
Vo 4
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil)
TDA9840
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH wM (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 7.62 0.30
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2.0 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-05-24
1998 Jul 03
23
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
TDA9840
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
1998 Jul 03
24
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
TDA9840
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1998 Jul 03
25
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA9840
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 Jul 03
26
Philips Semiconductors
Product specification
TV and VTR stereo/dual sound processor with digital identification and I2C-bus control
NOTES
TDA9840
1998 Jul 03
27
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
545104/00/03/pp28
Date of release: 1998 Jul 03
Document order number:
9397 750 03999

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